As semiconductor devices are continuously scaled down, the effective channel length of a gate becomes smaller. This may cause a punchthrough and a short channel effect at a transistor. In order to overcome these problems, an elevated source/drain has been suggested. The elevated source/drain is formed using a selective epitaxial growth (SEG) process to be higher than a surface of a semiconductor substrate. Thus, the short channel effect and the punchthrough can be prevented by forming a source/drain region having a shallow impurity-diffusing layer in the semiconductor substrate. Further, a silicide layer is formed by siliciding a silicon epitaxial layer to lower contact resistance and improve conductivity.
Unfortunately, the elevated source/drain suffers from the problems as follows:
First, the silicon epitaxial layer grows on the surface of the semiconductor substrate along a regular direction. Thus, a facet is formed in which an edge of the silicon epitaxial layer becomes thin. While siliciding the silicon epitaxial layer, a semiconductor substrate below a relatively thin facet is silicided to form a silicide layer deeply toward an inside of the semiconductor substrate at the edge of a source/drain region. As a result, an electric field is concentrated on the edge of the source/drain region which allows a leakage current to flow into the semiconductor substrate.
Second, a transistor connected to input and output terminals of a semiconductor component may be subjected to an electric shock caused by electrostatic discharge (ESD). Therefore, an ESD protection circuit is constructed at the input and output terminals. The ESD protection circuit includes transistors having a resistance to a high current and a high voltage. As a silicide layer formed at a source/drain region of these transistors is close to a gate electrode, local thermal damage occurs at a transistor junction, which an destroy the transistors. In order to achieve a ballasting effect, the silicide layer is disposed a predetermined distance apart from the gate electrode to prevent the destruction of the transistors.
FIG. 1 through FIG. 4 are cross-sectional views for explaining the problems of the prior art.
Referring to FIG. 1, a device isolation layer 102 is disposed at a predetermined region of a semiconductor substrate 100 to define an active region. A gate pattern 110 is formed at the active region, and includes a gate oxide layer 104, a gate electrode 106, and a gate capping insulating layer 108 that are sequentially stacked. Impurities are implanted into the active regions adjacent to opposite sides of the gate electrode to form a lightly doped diffusion layer 112.
Referring to FIG. 2, first and second insulating layers are sequentially, conformally formed on an entire surface of the resultant structure. The second insulating layer, the first insulating layer, and the gate capping insulating layer 108 are sequentially, anisotropically etched to form a first insulating layer pattern 114 and a second insulating layer pattern 116 that sequentially cover the sidewall of the gate electrode 106.
Referring to FIG. 3, using the gate electrode 106, the first insulating layer pattern 114 and the second insulating layer pattern 116 as an ion implanting mask, impurities are implanted into the active regions adjacent to opposite sides of the gate electrode 106 to form a heavily doped diffusion layer 120. As a result, LDD-type source/drain regions 127 are formed in the active regions adjacent opposite sides of the gate electrode 106. A silicon epitaxial layer 118 is grown on a top surface of the gate electrode 106 and on a semiconductor substrate 100 exposed after there side of the gate electrode 106. A facet 119 is formed at an edge of the epitaxial layer 118 adjacent the device isolation layer 102 or the first insulating layer.
Referring to FIG. 4, the silicon epitaxial layer 118 is silicided to form a gate silicide layer 118a and a source/drain silicide layer 118b on the gate electrode 106 and the source/drain region 127, respectively. Because of the facet 119 formed at the edge of the silicon epitaxial layer 118, the edge of the source/drain silicide layer 118b has a protrusion 122 that is protruded inwardly toward a semiconductor substrate 100 adjacent to the first insulating layer 114. When a voltage is applied at the source/drain region 127, an electric field is concentrated on the protrusion 122, which allows a leakage current to flow into the semiconductor substrate 100 from the source/drain region 127. The leakage current can deteriorate characteristics of a semiconductor device and interrupt normal operations thereof. A way of preventing the formation of the protrusion 122 is to form the silicon epitaxial layer 118 thickly. Generally, a silicon epitaxial layer is grown by sputtering. So, while growing the silicon epitaxial layer 118, silicon particles can attach to an external sidewall of the second insulating layer pattern 116. Following a silicidation process, the silicon particles can undesirably electrically connect the gate silicide layer 118a to the source/drain silicide layer 118b. This problem becomes worse with increase in thickness of the silicon epitaxial layer 118.